FIG. 1 is an idealized plan view of a portion of a silicon wafer 11, showing four separate circuits, 12a-12d. Separating these different circuits, some of which may be digital and some analog, is a barrier of some sort, shown schematically as isolating grid 13. The purpose of grid 13 is to electrically isolate these different circuits from one another for both AC (including RF) and DC.
Historically, several different technologies have evolved for the fabrication of the isolation grid, many of them being still in use today. The first isolation technology was a back-biased PN junction. Thus, if the main area 11 was P type, the material in 13 would be N type. While effective, this approach is limited mainly by the difficulty of making the grid 13 extend a sufficient depth below the silicon surface. In particular, technologies employed up till now are not able to uniformly dope the grid and cause it to extend all the way through the wafer to the far surface.
Other approaches, not based on PN junctions, include shallow trench isolation (STI) in which trenches are formed in the wafer surface and then filled with insulation. As with conventional PN junction approaches, fabrication of trenches that extend all the way to the far surface is not a practical proposition. This can be solved by using silicon on insulator (SOI) technology in which the silicon wafer is replaced by a thin sheet of silicon on a dielectric backing. While effective (except for RF circuits), SOI is an inherently expensive technology and lower cost means of forming isolating regions that extend all the way from one surface to the other are constantly being sought. The present invention describes a process and structure for accomplishing this goal.
A routine search of the prior art was conducted. The search revealed that most references have concentrated on use of a dielectric layer to achieve electrical isolation of devices. Several examples of device isolation using PN junctions were also found but none show isolating moats that extend the full thickness of a wafer.
Himi et al. (U.S. Pat. No. 5,650,354) describe a form of SOI in which N wells are isolated with either a buried layer of oxide or by being bonded directly to P type material. This approach, while effective, is expensive.
Iida et al. (U.S. Pat No. 5,644,157) also use buried dielectric sidewalls to provide isolation. Additional semiconducting layers are provided within the isolated area to further improve the breakdown characteristics of the device.
Harada et al. (U.S. Pat. No. 5,525,821) use buried insulation for the gate oxide layer of an IGBT but achieves circuit isolation by means of a buried P+ layer.
Mihara (U.S. Pat. No. 5,212,109) provides isolating barriers formed of amorphous or poly silicon. Because of the high concentration of recombination centers in these materials, charge carriers end up getting trapped inside the barrier layer instead of crossing it.
Josquin et al. (U.S. Pat. No. 5,151,382) provide a well of a first conductivity type in which devices are to be formed and surround it (sides and bottom) with materials of the other conductivity type. This reference is thus a classic example of PN junction isolation.